Parallel programming Optimization tricks

Comparision of 2 __m128i:

• SSE 4.1:

#define iszero(a) _mm_testz_si128(a, a)
#define isequal(a, b) _mm_testc_si128(_mm_cmpeq_epi32(a, b), gAllOnes)

• Others:

#define iszero(a) (_mm_movemask_epi8(_mm_cmpeq_epi32(a, _mm_setzero_si128())) == 0xffff)
#define isequal(a, b) (_mm_movemask_epi8(_mm_cmpeq_epi32(a, b)) == 0xffff)

Number of trailing zeros of an int:

• intrinsic: _bit_scan_forward()
• corresponding asm instruction: bsfl

Nehalem

Some features of Intel's Nehalem CPU architecture.


Turbo Boost:

• allow processors to operate above the rated frequency

• control by continual measurement of process temperature, current draw and power consumption

• upper limit of frequency controlled by:

• number of active(in “C0″ or “C1″ state) cores(dictates the upper limit)

• estimated current consumption

• estimated power consumption

• process temperature

• all active cores operate at the same frequency and voltage

• BIOS can enable/disable Turbo Boost

• ACPI awared OS need no change to support Turbo Boost

• OS should request the highest performance state(P0), should enable ACPI ?

• Software shows correct core frequency: i7z

Intelligent Power:

• adjust processor frequency when process is idle

Hyper-Threading:

• 2 threads per core

Quick Path:

• replace FSB

• up to 25.6 GB/s

• each processor has its own dedicated memory that it accesses directly through an integrated memory controller

• access the dedicated memory of another processor should go through QPI

SSE4:

• XML, text processing

Multi-level cache:

• Level 1: 32KB instruction cache, 32 KB data cache

• Level 2: 256KB per core, for data and instruction

• Level 3: cache shared across all cores

Benchmark Tool

Disk IO / File System performance: Bonnie++ , IOzone

Memory Bandwidth:  STREAM

FLOPS: HPL